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1. general description the 74alvch32973 is a 16-bit bus transcei ver and transparent d-type latch with 8 independent buffers with bus hold inputs and 3- state outputs. it featur es direction (1dir, 2dir), latch enable (1loe , 2loe ), transceiver output enable (1toe , 2toe ) and latch enable (1le, 2le) control inputs; four 8-bit transceiver ports (1an, 2an & 1bn, 2bn); two 8-bit d-type latch output ports (1qn, 2qn) and an 8-bit buffer with data inputs dn and outputs yn. the configuration of the control pins allows the device to be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver and one 16-bit latch. the 8-bit buffer functions independently of th e control inputs. the direction of data transmission between a and b is controlled by ndir and when ntoe is set high the a and b ports will assume a high -impedance off-state, they will be effectively isolated. when nle is high, data at the a inputs enter the latches. in this condition the latches are transparent, a q ou tput will change each time its corr esponding a- input changes. when nle is low the latches store the information th at was present at the inputs a set-up time preceding the high-to-low transition of nle. a high on nloe causes the q outputs to assume a high-impedance off-state. operation of the nloe input does not affect the state of the latches. 2. features and benefits ? wide supply voltage range from 1.2 v to 3.6 v ? complies with jedec standard jesd8-b ? cmos low power consumption ? direct interface with ttl levels ? all data inputs have bus hold ? output drive capability 50 ? transmission lines at 85 ? c ? current drive ? 24 ma at v cc = 3.0 v 74alvch32973 16-bit bus transceiver and tran sparant d-type latch with 8 independent buffers rev. 3 ? 17 january 2013 product data sheet
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 2 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 3. ordering information 4. functional diagram table 1. ordering information type number temperature range package name description version 74ALVCH32973EC ? 40 ? c to +85 ? c lfbga96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 ? 5.5 ? 1.05 mm sot536-1 fig 1. logic symbol
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" " " " " ! fig 2. bus hold circuit to internal circuit mna705 v cc data input
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 3 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 5. pinning information 5.1 pinning 5.2 pin description fig 3. pin configuration #$ % !! #$ #$ % !! #$ #$ % !! #$ #$ % !! #$ #$ % !! #$ #$ % !! #$ #$ % !! #$ #$ % !! #$ !&# " ' ($) table 2. pin description symbol ball description ntoe (n = 1 to 2) a3, j3 transceiver output enable input (active low) ndir (n = 1 to 2) a4, j4 direction control input (active high) nle (n = 1 to 2) h3, t3 latch enable input (active high) nloe (n = 1 to 2) h4, t4 latch output enable input (active low) 1a[0:7] a1, b1, c1, d1, e1, f1,g1, h1 data input/output d[0:7] a2, c2, e2, g2, j2, l2, n2, r2 data input 1b[0:7] a5, b5, c5, d5, e5, f5, g5, h5 data input/output 2b[0:7] j5, k5, l5, m5, n5, p5, r5, t5 data input/output y[0:7] b2, d2, f2, h2, k2, m2, p2, t2 data output 1q[0:7] a6, b6, c6, d6, e6, f6, g6, h6 data output 2a[0:7] j1, k1, l1, m1, n1, p1, r1, t1 data input/output 2q[0:7] j6, k6, l6, m6, n6, p6, r6, t6 data output gnd b3, b4, d3, d4, e3 , e4, g3, g4, k3, k4, m3, m4, n3, n4, r3, r4 ground (0 v) v cc c3, c4, f3, f4, l3, l4, p3, p4 supply voltage
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 4 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 6. functional description 6.1 function table [1] h = high voltage level; l = low voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; i = low voltage level one set-up time prior to the high-to-low le transition; ? = negative-going transition; z = high-impedance off-state; x = don?t care. [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. table 3. function table [1] inputs internal latches outputs nqn operating mode nloe nle nan l h l l l enable and read register (transparent mode) lhhh h l ? l l l latch and read register l ? hh h l l x no change no change hold mode h ? l l z latch register and disable outputs h ? hh z h h l l z enable register and disable outputs hhhh z h l x no change z hold mode and disable outputs table 4. function table [1] inputs outputs ntoe ndir nan nbn l l nan = nbn input l h input nbn = nan hxz z table 5. function table [1] input output dn yn ll hh
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 5 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] above 70 ? c the value of p tot derates linearly with 1.8 mw/k. 8. recommended operating conditions table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v i ik input clamping current v i <0v ? 50 - ma v i input voltage control inputs [1] ? 0.5 +4.6 v data inputs [1] ? 0.5 v cc +0.5 v i ok output clamping current v o >v cc or v o <0v - ? 50 ma v o output voltage [1] ? 0.5 v cc +0.5 v i o output current v o =0v tov cc - ? 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +85 ?c [2] -1 0 0 0m w table 7. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage maximum speed performance c l = 30 pf 2.3 - 2.7 v c l = 50 pf 3.0 - 3.6 v low voltage applications 1.2 - 3.6 v v i input voltage 0 - v cc v v o output voltage 0 - v cc v t amb ambient temperature in free air ? 40 - +85 ?c ? t/ ? v input transition rise and fall rate v cc = 2.3 v to 3.0 v 0 - 20 ns/v v cc = 3.0 v to 3.6 v 0 - 10 ns/v
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 6 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 9. static characteristics table 8. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit t amb = ? 40 ? c to +85 ?c v ih high-level input voltage v cc = 1.2 v v cc --v v cc = 1.8 v 0.7v cc 0.9 - v v cc = 2.3 v to 2.7 v 1.7 1.2 - v v cc = 2.7 v to 3.6 v 2.0 1.5 - v v il low-level input voltage v cc = 1.2 v - - 0 v v cc = 1.8 v - 0.9 0.2v cc v v cc = 2.3 v to 2.7 v - 1.2 0.7 v v cc = 2.7 v to 3.6 v - 1.5 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 ? a; v cc = 1.8 v to 3.6 v v cc ? 0.2 v cc -v i o = ? 6ma; v cc = 1.8 v v cc ? 0.4 v cc ? 0.1 - v i o = ? 6ma; v cc = 2.3 v v cc ? 0.3 v cc ? 0.08 - v i o = ? 12 ma; v cc = 2.3 v v cc ? 0.5 v cc ? 0.17 - v i o = ? 12 ma; v cc = 2.7 v v cc ? 0.5 v cc ? 0.14 - v i o = ? 18 ma; v cc = 2.3 v v cc ? 0.6 v cc ? 0.26 - v i o = ? 24 ma; v cc = 3.0 v v cc ? 1.0 v cc ? 0.28 - v v ol low-level output voltage v i =v ih or v il i o = 100 ? a; v cc = 1.8 v to 3.6 v - 0 0.20 v i o = 6 ma; v cc = 1.8 v - 0.09 0.30 v i o =6ma; v cc = 2.3 v - 0.07 0.20 v i o =12ma; v cc = 2.3 v - 0.15 0.40 v i o =12ma; v cc = 2.7 v - 0.14 0.40 v i o = 18 ma; v cc = 2.3 v - 0.23 0.60 v i o =24ma; v cc = 3.0 v - 0.27 0.55 v i i input leakage current v cc = 1.8 v to 3.6 v; v i =v cc or gnd - 0.1 5 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd v cc = 1.8 v to 2.7 v - 0.1 5 ? a v cc = 2.7 v to 3.6 v - 0.1 10 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc = 1.8 v to 2.7 v - 0.4 80 ? a v cc = 2.7 v to 3.6 v - 0.4 80 ? a ? i cc additional supply current v i =v cc ? 0.6 v; i o =0a; v cc = 2.7 v to 3.6 v per control input - 5 500 ? a per data i/o input - 150 750 ? a i bhl bus hold low current v cc = 2.3 v; v i =0.7v 45 - - ? a v cc = 3.0 v; v i =0.8v 75 150 - ? a
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 7 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers [1] all typical values are measured at t amb =25 ? c. 10. dynamic characteristics i bhh bus hold high current v cc = 2.3 v; v i =1.7v ? 45 - - ? a v cc = 3.0 v; v i =2.0v ? 75 ? 175 - ? a i bhlo bus hold low overdrive current v cc = 3.6 v 500 - - ? a i bhho bus hold high overdrive current v cc = 3.6 v ? 500 - - ? a c i input capacitance - 5.0 - pf c i/o input/output capacitance -8.0-pf table 8. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ [1] max unit table 9. dynamic characteristics at recommended operating conditions. voltages ar e referenced to gnd (ground = 0 v); test circuit figure 10 . symbol parameter conditions min typ [1] max unit t amb = ? 40 ? c to +85 ?c t pd propagation delay nan to nqn; see figure 4 [2] v cc = 1.2 v - 7.0 - ns v cc = 1.8 v 1.1 3.4 5.7 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.2 3.9 ns v cc = 2.7 v 1.0 2.7 3.8 ns v cc = 3.0 v to 3.6 v [4] 1.0 2.5 3.6 ns nle to nqn; see figure 5 [2] v cc = 1.2 v - 8.2 - ns v cc = 1.8 v 1.5 3.7 5.9 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.4 3.8 ns v cc = 2.7 v 1.0 2.7 4.3 ns v cc = 3.0 v to 3.6 v [4] 0.8 2.6 4.1 ns nan to nbn or nbn to nan; see figure 6 [2] v cc = 1.2 v - 5.9 - ns v cc = 1.8 v 1.4 3.0 4.3 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.0 3.8 ns v cc = 2.7 v 1.0 2.3 3.7 ns v cc = 3.0 v to 3.6 v [4] 1.0 2.2 3.4 ns dn to yn; see figure 7 [2] v cc = 1.2 v - 4.6 - ns v cc = 1.8 v 1.1 2.4 5.1 ns v cc = 2.3 v to 2.7 v [3] 0.7 1.7 3.7 ns v cc = 2.7 v 1.0 2.1 3.6 ns v cc = 3.0 v to 3.6 v [4] 0.9 1.8 3.1 ns
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 8 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers t en enable time nloe to nqn; see figure 8 [2] v cc = 1.2 v - 9.5 - ns v cc = 1.8 v 1.5 4.6 7.3 ns v cc = 2.3 v to 2.7 v [3] 1.0 3.0 5.2 ns v cc = 2.7 v 1.0 3.3 4.9 ns v cc = 3.0 v to 3.6 v [4] 1.0 2.7 4.3 ns ntoe to nan or nbn; see figure 8 [2] v cc = 1.2 v - 10.0 - ns v cc = 1.8 v 1.5 4.7 7.6 ns v cc = 2.3 v to 2.7 v [3] 1.0 3.2 5.7 ns v cc = 2.7 v 1.0 3.3 5.4 ns v cc = 3.0 v to 3.6 v [4] 1.0 2.7 4.4 ns ndir to nan or nbn; see figure 8 [2] v cc = 1.2 v - 7.0 - ns v cc = 1.8 v 1.5 3.5 7.6 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.7 5.2 ns v cc = 2.7 v 1.0 4.2 6.0 ns v cc = 3.0 v to 3.6 v [4] 1.0 3.4 5.0 ns t dis disable time nloe to nqn; see figure 8 [2] v cc = 1.2 v - 6.7 - ns v cc = 1.8 v 1.5 3.5 5.6 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.2 4.1 ns v cc = 2.7 v 1.0 3.4 4.7 ns v cc = 3.0 v to 3.6 v [4] 1.0 3.1 4.2 ns ntoe to nan or nbn; see figure 8 [2] v cc = 1.2 v - 7.0 - ns v cc = 1.8 v 1.5 3.6 7.6 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.6 5.2 ns v cc = 2.7 v 1.0 3.5 4.6 ns v cc = 3.0 v to 3.6 v [4] 1.0 3.2 4.3 ns ndir to nan or nbn; see figure 8 [2] v cc = 1.2 v - 7.2 - ns v cc = 1.8 v 1.5 3.7 7.6 ns v cc = 2.3 v to 2.7 v [3] 1.0 2.7 5.2 ns v cc = 2.7 v 1.0 4.0 6.0 ns v cc = 3.0 v to 3.6 v [4] 1.0 3.2 5.0 ns table 9. dynamic characteristics ?continued at recommended operating conditions. voltages ar e referenced to gnd (ground = 0 v); test circuit figure 10 . symbol parameter conditions min typ [1] max unit
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 9 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers [1] all typical values are measured at t amb =25 ? c. [2] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [3] typical values are measured at v cc = 2.5 v. [4] typical values are measured at v cc = 3.3 v. [5] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. t w pulse width nle high; see figure 5 v cc = 1.8 v 3.5 1.0 - ns v cc = 2.3 v to 2.7 v [3] 3.0 1.0 - ns v cc = 2.7 v 3.0 1.0 - ns v cc = 3.0 v to 3.6 v [4] 2.5 1.0 - ns t su set-up time nan to nle; see figure 9 v cc = 1.8 v 1.1 ? 0.1 - ns v cc = 2.3 v to 2.7 v [3] 1.1 ? 0.1 - ns v cc = 2.7 v 1.1 ? 0.1 - ns v cc = 3.0 v to 3.6 v [4] 1.1 ? 0.1 - ns t h hold time nan to nle; see figure 9 v cc = 1.8 v 1.3 0.1 - ns v cc = 2.3 v to 2.7 v [3] 1.6 0.2 - ns v cc = 2.7 v 1.6 0.4 - ns v cc = 3.0 v to 3.6 v [4] 1.3 0.2 - ns c pd power dissipation capacitance per latch or buffer; v i =gndtov cc ; v cc = 1.2 v to 3.6 v [5] q outputs enabled; a and b ports isolated; f i(nan) = 10 mhz; f i(nle) = 20 mhz; f i(nqn) = 10 mhz -26-pf a outputs enabled; q output disabled; f i(nan) = 10 mhz; f i(nbn) = 10 mhz -16-pf b outputs enabled; q output disabled; f i(nan) = 10 mhz; f i(nbn) = 10 mhz -16-pf y outputs enabled; a and b parts isolated; q output disabled; f i(dn) = 10 mhz; f i(yn) = 10 mhz -12-pf all outputs disabled; one nle input and one nan input switching; f i(nan) = 10 mhz; f i(nle) = 20 mhz; f i(nqn) = 0 mhz -18-pf q outputs disabled; a and b ports isolated; one nle input switching; f i(nan) = 0 mhz; f i(nle) = 20 mhz; f i(nqn) = 0 mhz -6-pf table 9. dynamic characteristics ?continued at recommended operating conditions. voltages ar e referenced to gnd (ground = 0 v); test circuit figure 10 . symbol parameter conditions min typ [1] max unit
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 10 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 11. waveforms measurement points are given in table 10 . v ol and v oh are typical output levels that occur with the output load. fig 4. propagation delay, input (nan) to data output (nqn) * +, ,+, ) ) #$ % % ( % ( % ( % ( % % measurement points are given in table 10 . v ol and v oh are typical output levels that occur with the output load. fig 5. propagation delay, latch enable input (nle) to data output (nqn), and pulse width 001aam012 v i t w t phl v m v m v m gnd v oh v ol nle input nqn output t plh v m v m measurement points are given in table 10 . v ol and v oh are typical output levels that occur with the output load. fig 6. propagation delay, input (nan, nbn) to data output (nbn,nan) mna477 nan, nbn input nbn, nan output t phl t plh gnd v i v m v m v oh v ol
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 11 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers measurement points are given in table 10 . v ol and v oh are typical output levels that occur with the output load. fig 7. propagation delay, input (dn) to data output (yn) * +, ,+, ) ) #$ % % ( % ( % ( % ( % % measurement points are given in table 10 . v ol and v oh are typical output levels that occur with the output load. fig 8. 3-state enable and disable times
)- )- % % . ,+, / 0 , +, / 0 ,+, 0*/ 0 ,+, 122&& &&221 ,+, #22&& &&22# 3 * +, % % % % !! % ( #$ #$ )- )- % ( % ( measurement points are given in table 10 . the shaded areas indicate when the input is per mitted to change for predictable output performance. fig 9. data setup and hold times for input (nan) to input (nle) #$ #$ % % * +, * +, , , % ( % (
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 12 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 12. test information table 10. measurement points supply voltage input output v cc v i v m v m v x v y 2.3 v to 2.7 v and < 2.3 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.7 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v test data is given in table 11 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 10. test circuit for measuring switching times v ext v cc v i v o mna616 dut c l r t r l r l g table 11. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 2.3 v to 2.7 v and < 2.3 v v cc ? 2.0ns 30pf 500 ? open 2 ? v cc gnd 2.7 v 2.7 v 2.5 ns 50 pf 500 ? open 2 ? v cc gnd 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf 500 ? open 2 ? v cc gnd
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 13 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 13. package outline fig 11. package outline sot536-1 (lfbga96) 0.8 a 1 ba 2 unit d y e references outline version european projection issue date 00-03-04 03-02-05 iec jedec jeita mm 1.5 0.41 0.31 1.2 0.9 5.6 5.4 y 1 13.6 13.4 0.51 0.41 0.1 0.2 e 1 4 e 2 12 dimensions (mm are the original dimensions) sot536-1 e 0.15 v 0.1 w 0 5 10 mm scale sot536-1 lfbga96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm a max. a a 2 a 1 detail x e e x d e a b c d e f h g j k l m p n r t 246 135 b a e 2 e 1 ball a1 index area ball a1 index area y y 1 c b c ac c b ? v m ? w m 1/2 e 1/2 e
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 14 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 14. abbreviations 15. revision history table 12. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test ttl transistor-transistor logic table 13. revision history document id release date data sheet status change notice supersedes 74alvch32973 v.3 20130117 product data sheet - 74alvch32973 v.2 modifications: ? table note of function table updated (l ow-to-high changed into high-to-low). 74alvch32973 v.2 20121108 product data sheet - 74alvch32973 v.1 modifications: ? function table updated. 74alvch32973 v.1 20120822 product data sheet - -
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 15 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74alvch32973 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3 ? 17 january 2013 16 of 17 nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74alvch32973 16-bit bus transceiver and transparant d-type latch; 8 buffers ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 january 2013 document identifier: 74alvch32973 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 12 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 15 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 contact information. . . . . . . . . . . . . . . . . . . . . 16 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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